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CT1820 Data Terminal Bit Processor for MIL-STD-1553 A & B
Features
* Performs Encoder, Decoder, Logic and Control functions of a Data Bus Terminal to MIL-STD-1553 specifications, including Address, Mode Code and Broadcast Decoding and Terminal Fail Safe * Flexibility - all control lines accessible * Parallel tri-state subsystem l/O bus compatible with both 16 bit and 8 bit systems * Dual rank l/O registers for versatile subsystem tlmlng X LA LE * Operates from +5VDC @ 40mA typical (25mA CT1820) F * Self-contained oscillator and clock driver * Look-ahead serial receive data output * Self-test, on-line wraparound, plus off-line capability 9001
B
A E RO
S
ISO
I NC .
1
C
General Description
E
RTIFIED
The CT1555-3/CT1820 Bit Processor Unit (BPU) is an advanced Hybrid Microcircuit that provides the interface between a MIL-STD-1553 Transceiver such as CT3231M or CT3232M, and the subsystem internal parallel data bus. The unit can be employed as the mux bus interface for Remote Subsystems or Master Terminal Bus Controllers, thus providing a common interface for all systems communicating over the bus. The unit places no restrictions on Command, Response or polling operations as it transfers all Command, Status and Data words from the bus to parallel output lines, together with error information, bus status and handshaking signals. It also contains 5 Bit Address Recognition, Broadcast and Mode Code Decode, Terminal Fail Safe Signal and Self Test. In the transmit mode, it accepts parallel data from the user and transmits Command, Status and Data words, under subsystem control, to the data bus. Positive handshaking signals provide logic control synchronisation between the unit and the subsystem for direct data flow. The hybrid is completely compatible with all the electrical and functional spec requirements of MIL-STD-1553 A & B.
43 DATA SELECT 2 45 46 47 48 50 44 41 42 54 56 56 53 43 43 43 LOAD DATA 2 LOAD DATA 1
DATA SELECT 1 7
2
3
4
5
6
(OPTIONAL) SERIAL INPUT
(MSB) D15
FIRST RANK REC'V REG DO - D7
SECOND RANK REC'V REG DO - D7
FIRST RANK XMT REG DO - D7
LATCH DATA 1
(LSB) D0
LATCH DATA 2
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
SECOND RANK XMT REG DO - D7
Vcc 1 +5V GND GND 11 34
FIRST RANK REC'V REG D8 - D15
SECOND RANK REC'V REG D8 - D15
FIRST RANK XMT REG D8 - D15
SECOND RANK XMT REG D8 - D15
CASE 20
36 32
SERIAL DATA OUT RT ENABLE (MSB) A4 BUILT IN TEST SELECT ADDRESS DECODE MANCHESTER DECODER & CONTROL LOGIC MANCHESTER ENCODER & CONTROL LOGIC DATA IN DATA IN 21 22
5 BIT ADDRESS
{
12 8 9 A1 10 13 (LSB) A0 A3 A2
BIT SELECT DATA OUT DATA OUT
19 25 26
39
BROADCAST
BROADCAST DECODE
FAIL SAFE TIMER & CONTROL
FAIL SAFE
15
SEND DATA ESCOUT SYNC SEL
27 28 24 23 35 38 30 29 18
40
MODE CODE
MODE CODE DECODE
ENC ENA OUTPUT INH MRST +5V OSC / CLOCK POWER OSC & CLOCK DRIVER XTAL CLOCK OUT
14 16 33 37 31
VALID WORD COMM/DATA SYNC DEC RST TAKE DATA DSC OUT
CLOCK IN
17
Figure 1 - Functional Diagram eroflex Circuit Technology - Data Bus Modules For The Future (c) SCDCT1820 REV D 6/25/99
RX DATA IN
32 25 33 1
TX DATA IN TX DATA IN
DATA OUT DATA OUT
25 DATA 26
TX DATA OUT DATA BUS TX DATA OUT
CT3231 T/R HYBRID
2 7 RX DATA OUT
CT1820 OR CT1553 BIT PROCESSOR
DATA IN 21 DATA IN 29 XTAL 12 MHz 22
16 BIT OR 8 BIT SUBSYSYEM
26 RX DATA IN 31
RX DATA 10 OUT
CONTROL
TX INHIBIT
Figure 2 - Typical MIL-STD-1553 Data Terminal Absolute Maximum Ratings
Parameter Supply Voltage Logic Input Voltage Logic Input Current Clock Output Current (Pin 18) Clock In (Pin 17) Storage Temperature Range Operating Case Temperature Range +7.0 -0.3 to +5.5 -20 to +4 15 -0.3 to VCC +0.3V -65 to +150 -55 to +125 Units V V mA mA V C C
Electrical Characteristics
(VCC = 5.0V 5%) Sym VIH VIL VOH VOL VIHC VILC VOHC VOLC lOC lOSC Parameter / Conditions Logic "1" Input Voltage Logic "0" Input Voltage Logic "1" Output Voltage Logic "0" Output Voltage Logic "1" Input Voltage (CLOCK) Logic "0" Input Voltage (CLOCK) Logic "1" Output Voltage (CLOCK) Logic "0" Output Voltage (CLOCK) Logic Supply Current Oscillator / Clock Supply Current
2
Min 2.0 -
Typ -
Max 0.7
Units V V
See Pin assignments and Loading See Pin assignments and Loading VCC-0.5 VCC-0.3 40 8 GND+0.5 GND+0.3 13 V V V V mA mA
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PIN ASSIGNMENTS AND LOADING
In the following table, the symbols are defined as follows: IIH= maximum input HIGH current with VIN = 2.5 volts IIL = maximum input LOW current with VIN = 0.4 volts IOH = maximum output HIGH current for VOUT = 2.5 volts minimum IOL = maximum output LOW current for VOUT = 0.4 volts maximum * Indicates use of an internal pull-up resistor
Pin No Name IIH (A) VCC D8 D9 D10 D11 D12 DATA SELECT 1 A3* A2* A1* GROUND A4* A0* VALID WORD FAIL SAFE COMM / DATA SYNC CLOCK IN CLOCK OUT S / T SELECT CASE DATA IN DATA IN 20 20 -0.4 -0.4 20 20 -0.4 -0.4 40 -0.8 30 0.003 -1000 1.0 20 -0.4 -400 -400 - 380 2.4 2.4 2.4 +100 +100 -3 -3 -1000 1.0 1.0 -400 -400 -400 4.0 4.0 4.0 4.0 4.0 4.0 -1500 -3.2 20 -0.4 Logic and power return MSB of 5 Bit ADDRESS INPUT LSB of 5 Bit ADDRESS INPUT A LOW on this output indicates receipt of avalid word A HIGH on this output indicates termination of a transmitted message that exceeds 768s. A HIGH on this output indicates COMMAND (or STATUS) word reception. A LOW indicates DATA word reception. Input for 12MHz clock (20pf load). Output of OSCILLATOR AND CLOCK DRIVER. A HIGH on this input sets the unit in the self test mode. CASE CONNECTION A HIGH on this input represents a positive state on the bus. A HIGH on this input represents a negative state on the bus. (Pins 21 and 22 must both be high when the bus is inactive.) A LOW on this input initiates a transmit cycle. Actuates COMMAND (or STATUS) sync for an input LOW and DATA sync for an input HIGH. -400 -400 -400 4.0 4.0 4.0 4.0 4.0 4.0 1.2 A HIGH on this output produces a positive state on the bus. A HIGH on this output produces a negative state on the bus. A HlGH on this output indicates data shifting during the transmit cycle. LOW to HIGH transitions on thls output during HIGH SEND DATA cause the transmit cycle data shifting to occur. A 12MHz (parallel resonant) crystal is connected between this pin and ground. / CLOCK -1000 1.2 -400 2.4 -1000 1.2 -400 4.0 1.2 4.0 +5V power for OSCILLATOR AND CLOCK POWER DRIVER. LOW to HIGH transitions on this output during LOW TAKE DATA cause receive cycle data shifting to occur. A HIGH on this output indicates reception of a valid COMMAND (or STATUS) word containing the terminalis address. It also resets the FAIL SAFE. 20 -1500 -0.4 -3.2 20 20 -0.4 -0.4 A LOW on this input applies the contents of the SECOND RANK REC'V REG to the D8-D15 I/O pins Part of 5 Bit ADDRESS INPUT 40 -0.4 -1000 2.4 20 -0.4 -1000 6.0 10.0 CT1555-3 IIL (A) CT1820 IOL (mA CT1820-2 IOL (mA) +5V Power Input Part of 16 Bit TRI-STATE l/O Description
IOH IOL IIH IIL IOH (A) (mA (A) (A) (A)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
23 24 25 26 27 28
ENC ENA SYNC SEL DATA OUT DATA OUT SEND DATA ESC OUT
20 20
-0.4 -0.4 360 360 380 1000 2.4 2.4 2.4 1.2
20 20
-0.4 -0.4
-1000 1.2
29 30 31 32
XTAL +5V OSC POWER DSC OUT RT ENABLE
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SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
Pin No
Name IIH (A) DEC RST 20
CT1555-3 IIL (A) -0.4
CT1820 IOL (mA
CT1820-2 IOL (mA)
Description
IOH IOL IIH IIL IOH (A) (mA (A) (A) (A) 20 -0.4
33
A LOW on this input (for 1s minimum) resets the decoder to a condition ready for a new word, resets the COMM / DATA SYNC output LOW, and resets the VALID WORD output HIGH. Logic and Power Return.
34 35 36 37 38
GROUND OUTPUT INH SERIAL DATA OUT TAKE DATA MRST 60 -1.2 20 -0.4 -400 -360 1.6 2.4 20 -0.4 20 -0.4 -400 -400 4.0 4.0 4.0 4.0
A LOW on this input holds output pins 25 and 26 LOW. The received serial data in NRZ format is available at this pin during LOW TAKE DATA. A LOW on this output indicates data shifting during the receive cycle. A LOW on this input (for 1s minimum) interrupts and clears the transmit cycle, resets the FAIL SAFE, and also performs the same functions as DEC RST. -400 4.0 4.0 A HIGH on this output indicates reception of a valid COMMAND (or STATUS) word containing all ONES in the address field. A LOW on this output indicates reception of a valid COMMAND (or STATUS) word containing all ONES or all ZEROS in the sub-address field. Part of 16 Bit TRI-STATE l/O
39
BROADCAST*
-300
1.6
40
MODE CODE*
-600
2.4
-600
6.0
6.0
41 42 43 44 45 46 47 48 49
D6 D7 DATA SELECT 2 D5 D0 D1 D2 D3 LATCH DATA 2
40
-0.4
-1000 2.4
20
-0.4 -1000 6.0
10.0
20 40
-0.4 -0.4 -1000 2.4
20 20
-0.4 -0.4 -1000 6.0 10.0
A LOW on this input applies the contents of the SECOND RANK REC'V REG to the D0-D7 I/O pins. Part of 16 Bit TRI-STATE l/O LSB of 16BIT TRI-STATE I/O Part of 16 Bit TRI-STATE l/O Part of 16 Bit TRI-STATE l/O Part of 16 Bit TRI-STATE l/O
20
-0.4
A HIGH on this input allows the l/O data on D0-D7 to appear at the output of the FIRST RANK XMT REG. A LOW on this input holds the register outputs in their last state. -1000 2.4 -1000 6.0 Part of 16 Bit TRl-STATE l/O A LOW on this input loads the D0-D7 data into the SECOND RANK XMT REG. A HIGH on this input then locks out the data inputs to permit serial shifting. A HIGH on this input allows the l/O data on D8-D15 to appear at the output of the FIRST RANK XMT REG. A LOW on this input holds the register outputs in their last state. 20 -0.4 A LOW on this input loads the D8-D15 data into the SECOND RANK XMT REG. A HIGH on this input then locks out the data inputs to permit serial shifting. -1000 6.0 10.0 Part of 16 Bit TRl-STATE l/O. OPTIONAL SERIAL INPUT.
50 51
D4 LOAD DATA 2
40 60
-0.4 -1.2
52
LATCH DATA 1
20
-0.4
53
LOAD DATA 1
60
-1.2
54 55 56
D13 D14 D15
40
-0.4
-1000 2.4
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SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
TRANSMIT CYCLE OPERATION
ENCODER SHIFT CLOCK (ESC) (see Figure 3) operates at the data rate (1MHz). A low at ENCODER ENABLE (ENC ENA) during a falling edge of ESC x starts the Transmit cycle, which lasts for twenty ESC clock periods. The SYNC SELECT (SYNC SEL) input is valid at the next low-to-high transition of ESC y. A high at SYNC SEL will produce a data sync, or a low will produce a command sync for that word. Parallel data must be stable at the second rank transmit register before SEND DATA goes high z. Since ENC ENA is not synchronous with ESC, the minimum time to z is 3sec from ENC ENA leading edge. The first-rank transmit register may be operated transparently (LATCH DATA always high), or may be used to hold data ready for transmission, independent of the activity on the 16-line subsystem l/O bus. As long as LATCH DATA is held high, data present on the subsystem l/O bus appears at the output of the first rank transmit register. Stable data may be latched and held at the first rank register output by bringing LATCH DATA low. Data to be transmitted may be latched any time before the low-to high transition of SEND DATA (SEND DATA, when appled to the LOAD DATA inputs, locks out the data inputs to the second rank transmit register.) For multiple word transmissions, the next word may be inputted and latched any time after z, but before the next low to-high transition of SEND DATA.
0 ESC 1 2 3 4 5 16 17 18
SEND DATA remains high for 16 ESC periods, during which the parallel transmit data is clocked to the MANCHESTER ENCODER z to {. After the sync and Manchester coded data are transmitted through the DATA OUT and DATA OUT outputs, the ENCODER adds on the parity bit for that word |. If the transmitted word is to be the last word of the transmission, ENC ENA must go high by | to prevent initiation of another transmit cycle. At any time, a low applied to OUTPUT INHIBIT will force both DATA OUT and DATA OUT to a low state without affecting any other operations. The entire transmit cycle may be interrupted and cleared by applying a minimum of 1sec negative pulse to the MASTER RESET (MRST) input. For 8-BlT I/O subsystems, D0 is tied to D8, D1 to D9, etc., through D7 tied to D15, and data is inputted in 8-BlT bytes by using LATCH DATA 1 and LATCH DATA 2 and / or LOAD DATA 1 and LOAD DATA 2 independently. For serial data applications, D15 input serves as the serial transmit input. With LOAD DATA 1 held low and LATCH DATA 1 held high, D15 input is applied to the ENCODERis serial data input. Inputted data must be at the ESC rate with the MSB starting at the low-to-high transition of SEND DATA. If a message length ever exceeds 768sec, the 768sec TIME OUT (FAIL SAFE) flag goes high, and DATA OUT and DATA OUT are both forced to a low state. This condition will remain until a valid command word (containing the terminalis address) is received or until MRST goes low.
19 0 1 2 3 4 5 16 17 18 19
ENC ENA
DON'T CARE
DON'T CARE
SYNC SEL
VALID
DON'T CARE
VALID
DON'T CARE
DATA SELECT
SEE TEXT
DEPENDS ON "LATCH" TIMING
DEPENDS ON "LATCH" TIMING
LATCH DATA
DON'T CARE
OPTIONAL NEXT-WORD LATCH
SEE TEXT
OPTIONAL NEXT-WORD LATCH
SEND DATA & LOAD DATA DATA OUT
1/2 SYNC 1/2 SYNC 15 14 13 2 1 0 P 1/2 SYNC 1/2 SYNC 15 14 13 2 1 0 P
DATA OUT
1/2 SYNC
1/2 SYNC
15
14
13
2
1
0
P
1/2 SYNC
1/2 SYNC
15
14
13
2
1
0
P
IF USED
1
2
3
4
5
Figure 3 - Transmit Cycle Timing
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SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
0
ENCODER SHIFT CLOCK
1
2
TE1
ENCODER ENABLE
TE3 TE2
SYNC SELECT
VALID
TE4
SEND DATA & LOAD DATA
TE5
TE6
LATCH DATA (IF USED)
TE7
PARALLEL DATA IN
TE8
TE9 TE10
DATA SELECT
TE11
Symbol TE1 TE2 TE3 TE4 TE5 TE6 TE7 TE8 TE9 TE10 TE11
Description ENCODER ENABLE SET-UP TIME ENCODER ENABLE PULSE WIDTH SYNC SELECT SET-UP TIME SYNC SELECT 'VALID' PULSE WIDTH SEND DATA DELAY LATCH DATA HOLD TIME LATCH DATA SET UP TIME LATCH DATA PULSE WIDTH LOW PARALLEL DATA 'VALID' WIDTH DATA SELECT DISABLE TIME DATA SELECT PULSE WIDTH HIGH
Min 100 180 190 150 25 50 50 75 25 100
Max 70 -
Units ns ns ns ns ns ns ns ns ns ns ns
Figure 4 - Encoder Timing Detail
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SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
RECEIVE CYCLE OPERATION
DECODER SHIFT CLOCK (DSC) (see Figure 5) operates at the data rate (1MHz). When the DECODER recognises a valid sync and two valid Manchester data bits x, a receive cycle is initiated. The new sync is indicated at the COMMAND/DATA SYNC (C/D SYNC) output and the TAKE DATA output goes low y. The C/D sync output will remain in its valid state until a new sync is detected on a subsequent word or until DECODER RESET (DEC RST) or MRST goes low. A low at DEC RST or MRST causes C/D SYNC to go low. TAKE DATA remains low for 16 DSC periods during which time the 16 serial data bits appear at the SERIAL DATA OUTPUT (SDO). This data is simultaneously loaded into the first-rank receive register. The low-to-high transition of TAKE DATA z makes the new data available at the output of the second-rank receive register. This data remains available until the next low-to-high transitions of TAKE DATA. It is not reset or cleared by any other signals. This data is applied to the D0 to D15 I/O
bus by setting DATA SELECT lines low. After all data has been loaded into the receive registers, the data is checked for odd parity. A low on VALID WORD (VW) output z, indicates successful reception of a word without any Manchester or parity errors. For consecutive word receptions, VW will go high again in 3 to 3.5s. In the absence of succeeding valid syncs, VW will return high in 20s. A DEC RST (low) at any time will reset VW high. All decoded commands, including RT ENABLE (address recognition), BROADCAST and MODE CODE are enabled internally by VW and remain valid only as long as VW is low. For 8-BIT l/O subsystems (D0 tied to D8, through D7 tied to D15), data may be extracted in 8 BIT bytes by selectively activating DATA SELECT 1 and DATA SEL.ECT 2. For serial data systems, SERIAL DATA OUTPUT is available at the DSC rate from y to z.
0 OSC DATA IN DATA IN TAKE DATA C/D SYNC SDO VW
1/2 SYNC
1
2
3
4
5
16
17
18
19
0
1
2
3
4
5
16
17
18
19
1/2 SYNC
15
14
13
2
1
0
P
1/2 SYNC
1/2 SYNC
15
14
13
2
1
0
P
1/2 SYNC
1/2 SYNC
15
14
13
2
1
0
P
1/2 SYNC
1/2 SYNC
15
14
13
2
1
0
P
FROM PREVIOUS WORD
VALID FOR CURRENT WORD
VALID FOR CURRENT WORD
UNDEFINED
15
4
3
2
1
0
UNDEFINED
15
4
3
2
1
0
FROM PREVIOUS WORD
DECODE COMMANDS (see text) SECOND-RANK REC'V REGISTER CONTENT DATA SELECT
NOT VALID
VALID
NOT VALID
VALID
FROM PREVIOUS WORD
NEW DATA
NEW DATA
OPTIONAL-HIGH = TRISTATE HI-Z AT D0 TO D15
OPTIONAL-HIGH = TRISTATE HI-Z AT D0 TO D15
1
2
3
4
Figure 5 - Receive Cycle Timing
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SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
4
DECODER SHIFT CLOCK
5
19
TD1
TAKE DATA
TD2
TD3
C/D SYNC LAST STATE NEW SYNC
TD4
VALID WORD LAST STATE
TD5
BROADCAST
TD6
RT ENABLE
TD7
MODE CODE DATA SELECT
TD8
TD9
PARALLEL DATA OUT NEW DATA
Symbol TD1 TD2 TD3 TD4 TD5 TD6 TD7 TD8 TD9
Description TAKE DATA RELAY ON TAKE DATA DELAY OFF SYNC DELAY VALID WORD DELAY BROADCAST DELAY RT ENABLE DELAY MODE CODE DELAY DATA SELECT INPUT DELAY PARALLEL DATA OUTPUT DELAY
Min 0 (Note 1) -
Max 125 125 50 125 70 100 100 50 (Note 2)
Units ns ns ns ns ns ns ns ns ns
Notes: 1. DATA SELECT may be applied at any tlme that the 16 line I/O is otherwise free. The parallel DATA OUT, however, is not 'NEWDATA' until 50ns after TAKE DATA goes high. 2. 180ns max for CT1555-3.
Figure 6 - Decoding Timing Detail
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SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
SELF TEST FUNCTION
A high on the S/T SELECT input sets the hybrid in the SELF TEST mode. In this mode, the DATA and DATA output lines are connected to the Decoder inputs so that the unit may operate in the "wraparound" mode without actually going through the data bus transceiver. Note that the DATA and DATA output lines are active in this mode and the S/T SELECT command must also be used to inhibit the data bus transmitter to prevent arbitrary transmission on the data bus.
clock or an external clock source. For internal clock operation, a 12MHz parallel-resonant fundamental-mode crystal must be connected from XTAL to ground. Power (+5V) must be applied to +5V OSC/CLOCK POWER and CLOCK OUT must be connected to CLOCK IN. For external clock operation, no power is applied to +5V OSC/CLOCK POWER and the external clock is applied to CLOCK IN (CLOCK OUT not connected). The external clock must be capable of driving a 20 picofarad load to within 0.5 volts of VCC and within 0.5 volts of ground with rise and fall times of less than 10 nanoseconds. Standard TTL levels are not satisfactory. For a normal 1MHz data rate, the clock frequency must be 12MHz.
TERMINAL FAIL SAFE
In order to satisfy the Terminal Fail Safe requirements of MIL-STD-1553B, the DATA and DATA output lines are continuously monitored for length of message. A transmitted message in excess of 768s sets the FAIL SAFE output high and terminates the transmission by setting both DATA and DATA output lines low. As a redundant safety factor, the FAlLSAFE output may be applied to the lNHlBlT input of the data bus transmitter (if so equipped). Further transmissions are prevented until the FAIL SAFE flag is reset either by reception of a valid command word containing the terminal address or by a negative pulse on the MRST input. Note: Transmissions containing gaps of 3s or less are considered continuous, even if the gap is caused by a MRST pulse.
FALSE RT ENABLE
Terminals that continuously monitor their own transmissions are subject to "END-AROUND" operation due to a false RT ENABLE. The terminal can erroneously interpret its own status word as a new command word. If no measures are taken to prevent or re-set RT ENABLE, it will remain high for 20s or until the DECODER recognises a new valid sync (whichever time is shorter). RT ENABLE may be inhibited by interrupting the RECEIVE CYCLE during a status word transmission. Inverted SEND DATA applied to DEC RST will prevent reception of the status word. If continuous monitoring is required, RT ENABLE may be reset immediately after it goes high by a 1s (minimum) low at DEC RST. The status word will then be available at the second-rank receive register.
TERMINAL ADDRESS LINES
The five-bit terminal address is set by hard wiring the 5-BlT ADDRESS lines. The hybrid contains internal pull-up resistors so that logic "1" lines may be left open circuited. Logic "0" lines must be grounded. In operation, RT ENABLE goes high when a valid command word containing the hard-wired address is received. See "RECEIVE CYCLE OPERATION" for timing.
OSCILLATOR AND CLOCK DRIVER
The hybrid may be operated with either the internal
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SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
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Ordering Information
Model Number
CT1820
Package
2.155" x 1.14" Metal Plug In
Plug-In Package Outline
2.155 MAX 1.900 48 49 TOP VIEW 1.155 29 28 .450 REF .900
56 1 20 .100 TYP
21
.200 MAX .175 MIN .018 DIA TYP .002
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Specifications subject to change without notice.
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